Defining detailed test plan and supporting verification team with debug.
Architecture and RTL coding of high-speed digital circuits, modeling of analog blocks.
Defining place and route constraints, supporting place-and-route team to debug STA issues.
Defining and debugging DFT structures in the designs for high DFT coverage.
Managing, reviewing, and tracking the design and verification tasks executed by teams at off-site locations.
Science Degree(s) plus at least 5 to 7 years of digital design and verification experience in the industry.
Hands on experience in architecting and designing high-speed digital circuits in Verilog and/or System Verilog, writing test plans and familiarity with code quality metrics.
Must have deep understanding of asynchronous clock crossings, DFT design methodologies, and synthesis implications of RTL.
Hi! How can we help you?
Click below button to start chat