Intern (technicaL-Engineering)

  • 1-5 Year
  • Mississauga
  •   Posted On: March 22, 2018
  •   Skills:  Perl, RTL, Unix Shell, UVM, VMM

Job Overview

Roles & Responsibilities

Seeking a highly motivated and innovative digital verification engineer with strong theoretical and practical background in high-speed data recovery circuits. Working as part of a highly experienced mixed-signal design team, the candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB 2/3 SERDES products. The position offers an excellent opportunity to work with an expert team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs.

Responsibilities include:

• Writing constrained-random SystemVerilog testbenches using UVM and VMM;
• Creating and analyzing functional coverage and assertion coverage, and analyzing code coverage;
• Defining and tracking verification testplans;
• Debugging RTL and gate-level simulation failures;
• SystemVerilog analog behavior modelling;
• Firmware debug

Candidates should have experience writing scripts in languages such as Perl and Unix shell.  The ideal candidate would be familiar with Verilog and SystemVerilog.

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