Intern (technicaL-Engineering)

  • 2-6 Year
  • Nepean
  •   Posted On: March 22, 2018
  •   Skills:  Perl, RTL, Unix Shell

Job Overview

Roles & Responsibilities

Responsibilities include:

• Writing constrained-random SystemVerilog testbenches using UVM and VMM;
• Creating and analyzing functional coverage and assertion coverage, and analyzing code coverage;
• Defining and tracking verification testplans;
• Debugging RTL and gate-level simulation failures;
• SystemVerilog analog behavior modelling;
• Firmware debug

Candidates should have experience writing scripts in languages such as Perl and Unix shell.  The ideal candidate would be familiar with Verilog and SystemVerilog.

Position Requirements:

Enrolled in Computer Engineering or Electrical Engineering program

Hi! How can we help you?

Click below button to start chat

Chat Icon
chat icon