R&d Sipi Engineer, Staff

  • 8-9 Year
  • Nepean
  •   Posted On: March 22, 2018
  •   Skills:  DDR, Ethernet, MATLAB, Python, SATA, TCL

Job Overview

Roles & Responsibilities

Responsible for modeling, simulating, analyzing signal and power integrity (SIPI), troubleshooting and reviewing interfaces interconnect and debugging circuits. This encompasses all aspects of physical interconnect in a system context, including silicon, package, PCB, connectors and components on multi-signal transmission line interfaces. Performs, verifies and documents interface SIPI analysis outcome as part of customer services. Carry out experiments to validate modeling and methodologies. Develop and document signal and power integrity requirements and flows for internal and external customer use.

Requirements:

BSEE+ 8 years of direct industry experience working in the following areas:
A working knowledge of circuit simulation tools such as Synopsys HSPICE and FINESIM is required.
Familiarity with both Windows and Linux operating system is required.
An understanding of basic circuit and transmission line theory is essential, as is familiarity with and a working knowledge of concurrent time and frequency-domain methods of analysis and characterization.
Ideal candidate possesses excellent communication skills, both verbal and written.

Knowledge on interface such as DDR (e.g. DDR3, LPDDR3, DDR4 and LPDDR4), PCIe (e.g. 3 and 4), Ethernet, SATA, for example, is desirable.
Some experience in programming languages such as Python, TCL and Matlab is desired.
Practical experience with package and PCB design, including 3D electro-magnetic field solvers such as Ansys SiWave/HFSS, with proven ability to create models of usable bandwidth up-to 20GHz is preferred.
Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills.
Prior knowledge and experience with CAD tool such as Synopsys Custom Designer is preferred.

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